feat(ssnpm): Add support for pointer masking - #354
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Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
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| #error "Ssnpm extension is not available for RV32. Please disable CPU_EXT_SSNPM." | ||
| #elif !defined(CPU_EXT_SSNPM_PMM_MODE) | ||
| #error "Ssnpm extension PMM mode is not defined. Please define CPU_EXT_SSNPM_PMM_MODE." | ||
| #else |
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I don't think these checks should be here. What I'd suggest is to have a private function vmm_arch_config_ssmpm and then an if (CPU_HAS_EXT(...)) vmm_arch_config_ssmpm().
| switch (CPU_EXT_SSNPM_PMM_MODE) { | ||
| case HENVCFG_PMM_DISABLED: | ||
| if (cpu_is_master()) { | ||
| WARNING("Ssnpm extension is enabled but PMM mode is set to disabled.\r\n"); |
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Should actually be "extension is present". But I don't believe this is worth it. I don't think we should allow the configruation in this way. Either we: (i) simply disable support for the extension for now, or (ii) allow to set this in the config in a config global .arch field (i believe we have to add this) (e.g., .arch.npm_mode) or (ii) allow to set the mode per vm, in the a vm config arch field (e.g., arch.npm_mode field)
| } | ||
| } | ||
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| csrs_henvcfg_set(pmm_val); |
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To make sure we do this cleanly dont we first need to csrs_henvcfg_clear(HENVCFG_PMM_MSK) ?
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Summary
Add initial RISC-V
Ssnpmsupport for programming the guest-visible PMM mode.This change:
HSTATUS_HUPMMfield definitionshenvcfgduring hypervisor initwhen
CPU_EXT_SSNPMis enabledCPU_EXT_SSNPMCPU_EXT_SSNPM_PMM_MODEDependency
This PR depends on:
It is intended to be reviewed and merged on top of that series, since it builds
on the related RISC-V extension plumbing already introduced there.
Implementation
The patch:
HSTATUS_HUPMMfield definitions in the RISC-V CSR headervmm_arch_init()to configure PMM mode whenCPU_EXT_SSNPMis enabledSsnpmis enabled and which PMM modeBao should advertise
The following PMM modes are supported:
HENVCFG_PMM_DISABLEDHENVCFG_PMM_PMLEN_7HENVCFG_PMM_PMLEN_16On RV32, the build fails explicitly since
Ssnpmis not available there.Requirements to run
Running this support requires coordinated changes across Bao, the guest DT, and
QEMU.
Bao configuration
Enable cache-maintenance support in the Bao platform configuration for:
qemu-riscv32-virtqemu-riscv64-virtSet:
CPU_EXT_SSNPM = 1CPU_EXT_SSNPM_PMM_M = HENVCFG_PMM_PMLEN_7)Linux / Device Tree
It must also advertise the extensions in
riscv,isa.For RV32:
riscv,isa = "rv32imafdch_ssnpm_zicbom_zicboz_zicbop_zicntr_zicsr_zifencei_sstc";For RV64:
riscv,isa = "rv64imafdch_ssnpm_zicbom_zicboz_zicbop_zicntr_zicsr_zifencei_sstc";QEMU
A QEMU version with
ssnpmsupport is required, setssnpm=trueon the `cpu.https://github.com/ninolomata/qemu-bao/tree/riscv-rv32-henvcfg-stateen-fixesbao-demos(QEMU 10.0.2)